1. Field of the Invention
The present invention relates to a data processing system realizing a high processing performance by a high parallel processing mechanism, more particularly, it relates to a data processing system capable of executing plural instruction in parallel.
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of a typical pipe line processing mechanism of a conventional data processing system.
The pipe line processing mechanism of the data processing system shown in FIG. 1 is constituted by six pipe line stages consisting of an instruction fetch (IF) stage 91 for fetching instruction data, an instruction decoding (D) stage 92 for analyzing instruction data, an address calculation (A) stage 93 for executing operand address calculation, an operand fetch (F) stage 94 for fetching operand data, an execution (E) stage 95 for data processing and an operand writing (W) stage 96 for writing operand data.
In such a pipe line processing mechanism of the conventional data processing system, different instructions can be processed simultaneously in each stage. However, when conflicts occur with respect to the operand access and memory access, processings in the stage with a low priority are interrupted till the conflicts are settled.
As described above, in the data processing system designed for pipe line processing, by dividing the processing into plural stages according to the data processing flow and operating each of the stages simultaneously, a mean processing time necessary for one instruction is shortened to improve the performance as a whole.
An example of data processing system which is made highly efficient by processing the plural instructions simultaneously by the pipe line processing is disclosed in U.S. Pat. No. 4,402,042 "MICROPROCESSOR SYSTEM WITH INSTRUCTION PRE-FETCH".
However, in the data processing system capable of executing up to only one instruction in one machine cycle, the processing performance is restricted by the operating frequency. In order to solve this problem, a plurality of arithmetic units are provided to execute plural instructions in parallel.
For example, in a data processing system called IBM System/360 Model 91, by providing a plurality of adders, multipliers and dividers and adding the function called a "reservation" "station" to each of the arithmetic units, the instructions are subjected to passing control to improve the processing speed.
The processing is described particularly in "Computer Structures: Principles and Examples" by Daniel P. Siewiorek, C. Gordon Bell and Allen Newell, McGraw-Hill Book Company, PP. 295-298 (1982).
Also, in a microprocessor MC 88100 by Motorola Inc., by providing a mechanism called "register scoreboarding", conflicts occurred between registers used by a plurality of execution units are detected and a parallel processing sequence is controlled. This is described particularly in "32-bit Microprocessor, Parallel Arithmetic Processings improve Performance", Nikkei Electronics, No. 448, PP. 145 through 149 (1988).
Furthermore, there is also such a case that, by providing an exclusive executing unit for simple arithmetic and logic operation instructions, which is operable independently of usual executing units and having no memory operand, the instructions are passed and controlled. The details are disclosed in "Study on CPU Architecture of a 32-bit Microprocessor TX3 based on TRON Specification" by T. Miyamori et al, Shingaku Technical Review, Vol. 87, No. 422, CPSY 87-53, PP. 31 through 36 (1988).
In a data processing system called i80860 by Intel Corp. an integer unit, a floating-point adder and a floating-point multiplier are independent and operable simultaneously. When the integer instruction and floating point instruction are in series, the two instructions may be decoded and executed simultaneously. The details are given in "A 1,000,000 Transistor Microprocessor" by Leslie Kohn and Sai-Wai Fu, ISSCC Digest of Technical Papers, PP. 54 and 55 (1989).
In this way, in the conventional data processing system, the improvement of processing speed is intended by executing the instructions in parallel and controlling the passing of the instructions. However, the detection of a conflict of operands among a plurality of instructions and the execution control including the avoidance of malfunctions are greatly complicated.
In the case where an exception occurs while passing processing of instructions is executed, greatly complicated control is necessary after exceptional processing in order to return the state of the data processing system to the state when the exception was detected and operate the data processing system compatibly.
The conventional data processing system, as aforementioned, has a problem that the execution of a plurality of instructions in parallel makes the execution control greatly complicated and makes the amount of logic for realizing their functions increase largely.
Also a problem occurs that it is very difficult to return the data processing system to the state when the exception was detected after the exceptional processing, in the case where the exception occurs in midway of instruction processing.